Conventional digital desynchronizers have hardened or fixed tolerances on jitter leakage within the system and thus require a tighter restriction around a fixed leakage rate with fixed thresholds when accumulating the jitter. Such restriction results in an output that, though may be within a desired specification requirement of the system, produces output data that cannot have programmability to the rate of smoothness or has a method of programming the amount of smoothness. Further, conventional digital desynchronizers are not adaptable in response to changes in standards and would have to be redesigned to meet such changes. Therefore, it is desirable to have a digital desynchronizer that produces smooth outputs and can adjust to changes in standards or system requirements without significant redesign effort.